DM9161A
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
1. General Description
The DM9161A is a physical layer, single-chip, and low power transceiver for 100BASE-TX and 10BASE-T operations. On the media side, it provides a direct interface either to Unshielded Twisted Pair Category 5 Cable (UTP5) for 100BASE-TX Fast Ethernet, or UTP5/UTP3 Cable for 10BASE-T Ethernet. Through the Media Independent Interface (MII), the DM9161A connects to the Medium Access Control (MAC) layer, ensuring a high inter operability from different vendors.
TheDM9161A uses a low power and high performance advanced CMOS process. It contains the entire physical layer functions of 100BASE-TX as defined by IEEE802.3u, including the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), Twisted Pair Physical Medium Dependent Sublayer (TP-PMD), 10BASE-TX Encoder/Decoder (ENC/DEC), and Twisted Pair Media Access Unit (TPMAU). The DM9161A provides a strong support for the auto-negotiation function, utilizing automatic media speed and protocol selection. Furthermore, due to the built-in wave shaping filter, the DM9161A needs no external filter to transport signals to the media in 100BASE-TX or 10BASE-T Ethernet operation.
2. Features
* Fully comply with IEEE 802.3 / IEEE 802.3u 10Base-T/ 100Base-TX, ANSI X3T12 TP-PMD 1995
standard Support MDI/MDI-X auto crossover function (Auto-MDI)
* Support Auto-Negotiation function, compliant with IEEE 802.3u
* Fully integrated Physical layer transceiver On-chip filtering with direct interface to magnetic transformer
* Selectable repeater or node mode
* Selectable MII or RMII (Reduced MII) mode for 100Base-TX and 10Base-TX. Selectable MII or
GPSI (7-Wired) mode for 10Base-T
* Selectable full-duplex or half-duplex operation MII management interface with maskable interrupt
output capability
* Provide Loopback mode for easy system diagnostics
* LED status outputs indicate Link/ Activity, Speed10/100 and Full-duplex/Collision. Support
Dual-LED optional control
* Single low power Supply of 3.3V with an advanced CMOS technology
* Very Low Power consumption modes:
● Power Reduced mode (cable detection)
● Power Down mode
● Selectable TX drivers for 1:1 or 1.25:1 transformers for additional power reduction.
1: 1 transformers only when HP Auto-MDIX Enable .
* Compatible with 3.3V and 5.0V tolerant I/Os
* 48-pin LQFP
3. Block Diagram
4. Pin Configuration:
Absolute Maximum Ratings ( 25°C )
| Symbol | Parameter | Min. | Max. | Unit | Conditions |
| DVDD | Supply Voltage | -0.3 | 3.6 | V | |
| VIN | DC Input Voltage (VIN) | -0.5 | 5.5 | V | |
| VOUT | DC Output Voltage(VOUT) | -0.3 | 3.6 | V | |
| Tstg | Storage Temperature Rang (Tstg) | -65 | +150 | °C | |
| Tc | Case Temperature | 0 | 85 | °C | @Ta=0 ~ 70℃ |
| LT | Lead Temp. (TL, Soldering, 10 sec.) | -- | 235 | °C | DM9161AE |
| LT | Lead Temp. (TL, Soldering, 10 sec.) | -- | 260 | °C | DM9161AEP |
Product Tags:
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10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver DM9161AEP Images
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